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Integrated Circuit Systems, Inc.
ICS93716
Low Cost DDR Phase Lock Loop Clock Driver
Recommended Application: DDR Clock Driver Product Description/Features: * Low skew, low jitter PLL clock driver * I2C for functional and output control * Feedback pins for input to output synchronization * Spread Spectrum tolerant inputs Switching Characteristics: * PEAK - PEAK jitter (66MHz): <75ps * CYCLE - CYCLE jitter (>100MHz):<65ps * OUTPUT - OUTPUT skew: <100ps * Output Rise and Fall Time: 550ps - 950ps
Pin Configuration
CLKC0 CLKT0 VDD CLKT1 CLKC1 GND SCLK CLK_INT CLK_INC VDDA GND VDD CLKT2 CLKC2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND CLKC5 CLKT5 CLKC4 CLKT4 VDD SDATA FBINC FBINT FB_OUTT FB_OUTC CLKT3 CLKC3 GND
28-Pin SSOP and TSSOP
Functionality
INPUTS AVDD CLK_INT 2.5V (nom) 2.5V (nom) 2.5V (nom) L H <20MHz L H H L CLK_INC CLKT CLKC H L L H Z L H H L Z H L OUTPUTS FB_OUTT FB_OUTC L H Z L H H L Z H L PLL State on on off Bypassed/off Bypassed/off
Block Diagram
GND GND
FB_OUTT FB_OUTC
SCLK SDATA
Control Logic
CLKT0 CLKC0 CLKT1 CLKC1 CLKT2 CLKC2
FB_INT FB_INC CLK_INC CLK_INT
CLKT3 CLKC3
PLL
CLKT4 CLKC4 CLKT5 CLKC5
0420G--04/07/05
ICS93716
ICS93716
Pin Descriptions
PIN NUMBER 6, 11, 15, 28 PIN NAME GND TYPE PWR OUT OUT PWR Ground "Complementar y" clocks of differential pair outputs. "Tr ue" Clock of differential pair outputs. Power supply 2.5V DESCRIPTION
27, 25, 16, 14, 5, 1 CLKC(5:0) 26, 24, 17, 13, 4, 2 CLKT(5:0) 3, 12, 23 7 8 9 10 18 VDD
SCLK
CLK_INT CLK_INC VDDA FB_OUTC
IN
IN IN PWR OUT
Clock input of I2C input, 5V tolerant input
"True" reference clock input "Complementar y" reference clock input Analog power supply, 2.5V "Complementar y" Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INC. "True" " Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INT. "True" Feedback input, provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error. "Complementar y" Feedback input, provides signal to the internal PLL for synchronization with CLK_INC to eliminate phase error.
19 20 21 22
FB_OUTT FB_INT FB_INC
OUT IN IN
SDATA
IN
Data input for I2C serial input, 5V tolerant input
0420G--04/07/05
2
ICS93716
Byte 0: Output Control (1= enable, 0 = disable)
Byte 1: Output Control (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 2, 1 4, 5 13, 14 26, 27 24, 25
PWD 1 1 1 1 1 1 1 1
DESCRIPTION CLKT0, CLKC0 CLKT1, CLKC1 Reserved Reserved CLKT2, CLKC2 CLKT5, CLKC5 Reserved CLKT4, CLKC4
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 17, 16 -
PWD X 1 X X X X X X
DESCRIPTION Reserved CLKT3, CLKC3 Reserved Reserved Reserved Reserved Reserved Reserved
Byte 2: Reserved (1= enable, 0 = disable)
Byte 3: Reserved (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# -
PWD X X X X X X X X
DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reser ved
BIT PIN# PWD Bit 7 X Bit 6 X Bit 5 X Bit 4 X Bit 3 X Bit 2 X Bit 1 X Bit 0 X
DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reser ved
Byte 4: Reserved (1= enable, 0 = disable)
Byte 5: Reserved (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# -
PWD X X X X X X X X
DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reser ved
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# PWD 0 0 0 0 0 1 1 0
DESCRIPTION Reser ved (Note) Reser ved (Note) Reser ved (Note) Reser ved (Note) Reser ved (Note) Reser ved (Note) Reser ved (Note) Reser ved (Note)
Note: Don't write into this register, writing into this register can cause malfunction
0420G--04/07/05
3
ICS93716
Absolute Maximum Ratings
Supply Voltage (VDD & AVDD) . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . -0.5V to 4.6V GND - 0.5V to VDD + 0.5V 0C to +85C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, RL = 120, CL=15pF (unless otherwise stated) PARAMETER Input High Current Input Low Current Operating Supply Current Input Clamp Voltage High-level output voltage Low-level output voltage SYMBOL CONDITIONS I IH V I = V DD or GND I IL V I = V DD or GND IDD2.5 RL = 120, CL = 0pf @ 170MHz IDDPD VIK V OH V OL CL = 0pf V DDQ = 2.3V Iin = -18mA IOH = -1 mA IOH = -12 mA IOL=1 mA IOL=12 mA V I = GND or VDD V OUT = GND or VDD MIN 5 TYP MAX 5 250 65 VDD - 0.1 1.7 0.1 0.6 3 3 350 90 -1.2 UNITS A A mA mA V V V V V pF pF
CIN Input Capacitance1 1 COUT Output Capacitance 1 Guaranteed by design at 233MHz, not 100% tested in production.
0420G--04/07/05
4
ICS93716
DC Electrical Characteristics (see note1)
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER Supply Voltage Low level input voltage SYMBOL V DDQ, AVDD VIL CONDITIONS MIN 2.3 TYP 2.5 0.4 MAX 2.7 V DD/2 - 0.18 0.7 2.1 5 V DD + 0.3 V DD + 0.6 V DD + 0.6 VDD/2 + 0.15 VDD/2 0.1 0 VDD/2 + 0.2 5 85 UNITS V V V V V V V V V V A C
High level input voltage DC input signal voltage (note 2) Differential input signal voltage (note 3) Output differential crossvoltage (note 4) Input differential crossvoltage (note 4) High Impedance Output Current Operating free-air temperature
VIH VIN
CLK_INT, CLK_INC, FB_INC, FB_INT SCLK, SDATA -0.3 CLK_INT, CLK_INC, FB_INC, VDD/2 + 0.18 FB_INT SCLK, SDATA 1.7 -0.3 DC - CLK_INT, CLK_INC, FB_INC, FB_INT AC - CLK_INT, CLK_INC, FB_INC, FB_INT 0.36 0.7 VDD/2 - 0.15 V DD/2 - 0.2 VDD=2.7V, VOUT=VDD or GND
VID
V OX VIX IOZ TA
Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC excursion of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VTR is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of VDD and is the voltage at which the differential signal crosses.
0420G--04/07/05
5
ICS93716
Timing Requirements
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, RL = 120, CL=15pF (unless otherwise CONDITIONS PARAMETER SYMBOL MIN MAX UNITS Max clock frequency 3 Application Frequency Range3 Input clock duty cycle CLK stabilization freqop freqApp dtin TSTAB 33 60 40 233 170 60 100 MHz MHz % s
Switching Characteristics
TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, RL = 120 , CL=15pF (unless otherwise stated) PARAMETER Low-to high level propagation delay time High-to low level propagation delay time Duty Cycle Input clock slew rate SYMBOL t PLH1 t PHL1 DC t sl(I) t cyc -t cyc t cyc -t cyc CONDITION CLK_IN to any output CLK_IN to any output 49 1 MIN TYP 5.5 5.5 51 4 65 75 150 100 950 MAX UNITS ns ns % v/ns ps ps ps ps ps
100MHz < f < 170MHz 50 Cycle to Cycle Jitter1 f=66MHz 72 Cycle to Cycle Jitter1 4 -150 0 Phase error t(phase error) 75 Output to Output Skew t skew See figure 8 550 Rise Time, Fall Time t r, t f Notes: 1. Refers to transition on noninverting output in PLL bypass mode. 2. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle=twH/tc, were the cycle (tc) decreases as the frequency goes up. 3. Switching characteristics guaranteed for application frequency range. 4. Static phase offset shifted by design.
0420G--04/07/05
6
ICS93716
Parameter Measurement Information VDD V(CLKC)
R = 60
R = 60 VDD /2 V(CLKC) ICS93716 GND Figure 1. IBIS Model Output Load VDD/2 ICS93716 Z = 60 C = 15 pF -VDD/2 R = 10 Z = 50 SCOPE
R = 50 V(TT) Z = 60 R = 10 Z = 50
C = 15 pF -VDD/2 -VDD/2 NOTE: V(TT) = GND Figure 2. Output Load Test Circuit
R = 50 V(TT)
YX, FB_OUTC YX, FB_OUTT tc(n) tc(n+1) tjit(cc) = tc(n) tc(n+1) Figure 3. Cycle-to-Cycle Jitter
0420G--04/07/05
7
ICS93716
Parameter Measurement Information CLK_INC CLK_INT
FB_INC FB_INT
t( ) n
n=N t( ) n 1 t( )= N (N is a large number of samples) Figure 4. Static Phase Offset
t ( ) n+1
YX# YX
YX, FB_OUTC YX, FB_OUTT t(skew) Figure 5. Output Skew
YX, FB_OUTC YX, FB_OUTT YX, FB_OUTC YX, FB_OUTT
tC(n)
1 fO t(jit_per) = tc(n) - 1 fO Figure 6. Period Jitter
0420G--04/07/05
8
ICS93716
Parameter Measurement Information YX, FB_OUTC YX, FB_OUTT
t jit(hper_n) 1 fo t jit(hper_n+1)
tjit(hper) = t jit(hper_n)
-
1 2xfO
Figure 7. Half-Period Jitter
80%
80% VID, VOD
Clock Inputs and Outputs
20% tslr tslf
20%
Figure 8. Input and Output Slew Rates
0420G--04/07/05
9
ICS93716
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
0420G--04/07/05
10
ICS93716
N
c
L
INDEX AREA
E1
E
12 D
A2 A1
A
In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -2.00 -.079 A1 0.05 -.002 -A2 1.65 1.85 .065 .073 b 0.22 0.38 .009 .015 c 0.09 0.25 .0035 .010 SEE VARIATIONS SEE VARIATIONS D E 7.40 8.20 .291 .323 E1 5.00 5.60 .197 .220 0.65 BASIC 0.0256 BASIC e L 0.55 0.95 .022 .037 SEE VARIATIONS SEE VARIATIONS N 0 8 0 8 VARIATIONS N 28
10-0033
-Ce
b SEATING PLANE .10 (.004) C
D mm. MIN 9.90 MAX 10.50 MIN .390
D (inch) MAX .413
Reference Doc.: JEDEC Publication 95, MO-150
Ordering Information
ICS93716yFLF-T
Example:
ICS XXXXX y F LF - T
Designation for tape and reel packaging Annealed Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS, AV = Standard Device
0420G--04/07/05
11
ICS93716
N
c
L
SYMBOL A A1 A2 b c D E E1 e L N aaa VARIATIONS N 28
10-0039
INDEX AREA
E1
E
12 D
a
A2 A1
A
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX -1.20 -.047 0.05 0.15 .002 .006 0.80 1.05 .032 .041 0.17 0.27 .007 .012 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS 8.10 BASIC 0.319 BASIC 6.00 6.20 .236 .244 0.65 BASIC 0.0256 BASIC 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS 0 8 0 8 -0.10 -.004
-Ce
b SEATING PLANE
D mm. MIN 9.60 MAX 9.80 MIN .378
D (inch) MAX .386
aaa C
Reference Doc.: JEDEC Publication 95, MO-153
6.10 mm. Body, 0.65 mm. pitch TSSOP (25.6 mil) (240 mil)
Ordering Information
ICS93716yGLF-T
Example:
ICS XXXXX y GLF - T
Designation for tape and reel packaging Annealed Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS, AV = Standard Device
0420G--04/07/05
12

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